This invention relates to dynamic random access memories (DRAMs) and in particular to a boosted word line power supply charge pump and regulator for establishing word line voltage.
High density commercial DRAMS typically use capacitive pump voltage boosting circuits for providing sufficiently high voltage to drive DRAM word lines. Regulation of the voltage has been poor, and danger exists of generating voltages above the limits imposed by reliability requirements of the device technology. Such circuits, where a supply voltage of Vdd is present, generate a maximum achievable voltage of 2Vddxe2x88x92Vtn where Vtn is the threshold voltage of an N-channel field effect transistor (FET).
FIG. 1 illustrates a voltage boosting circuit according to the prior art and FIG. 2 illustrates clock signal waveforms used to drive the circuit.
A pair of N-channel transistors 1 and 2 are cross-coupled to form a bistable flip-flop, the sources of the transistors being connected to voltage rail Vdd. The drain of each transistor, is connected to the gate of the respective other transistor, and form nodes 3 and 4 which are connected through corresponding N-channel transistors 5 and 6 configured as diodes, to one terminal of a capacitor 7. The other terminal of capacitor 7 is connected to ground.
A clock source is connected through an inverter 8 and via capacitor 9 to node 4, and another clock source is connected through an inverter 10 through capacitor 11 to node 3.
The clock source voltage at the output of inverter 8 is shown as waveform xcfx862, varying between voltages Vdd and Vss, and the clock source output at the output of inverter 10 is shown as waveform xcfx861, varying between the voltages Vdd and Vss.
The output terminal of the circuit supplies the voltage Vpp at the junction of the capacitor 7 and transistors 5 and 6.
Operation of the above-described circuit is well known. As the levels of xcfx861 and xcfx862 vary as shown in FIG. 2, capacitors 9 and 11 alternately charge between Vss and Vdd and discharge to capacitor 7. The maximum achievable voltage at the output terminal is 2Vddxe2x88x92Vtn, where Vtn is the threshold of operation of either of transistors 5 or 6.
It should be noted that the external supply voltage Vdd can vary between limits defined in the device specification, and also as a result of loading, both static and dynamic of other circuits using the same supply. The threshold voltage Vtn is sensitive to variations in semiconductor processing, temperature and chip supply voltage, and this contributes to significant variation in the boosted supply. Finally the boosted Vpp supply itself varies as a function of load current drawn from capacitor 7. Therefore the voltage at the output terminal, which is supposed to provide a stable word line voltage can vary substantially from the ideal. For example, if Vdd is excessively high, this can cause the output voltage to soar to a level which could be damaging to word line access transistor gate insulation, damaging the memory. If Vdd is low, it is possible that insufficient output voltage could be generated to drive the memory cell access transistors, making memory operation unreliable.
The present invention is a circuit for providing an output voltage which can be used to drive memory word lines which can be as high as 2Vdd; it does not suffer the reduction of Vtn of the prior art circuit. Thus even if Vdd is low, the word line driving voltage even in the worst case would be higher than that of the prior art, increasing the reliability of operation of the memory.
The above is achieved by fully switching the transistors in a boosting circuit, rather than employing N-channel source followers as xe2x80x9cdiodesxe2x80x9d. This eliminates reduction of the boosting voltage by Vtn.
Another embodiment of the invention is a circuit for detecting the required word line driving voltage and for regulating the voltage boosting pump by enabling the pump to operate if the boosted voltage is low, causing the word line driving voltages to increase, and inhibiting the pump if the voltage reaches the correct word line voltage. This is achieved by utilizing a sample transistor which matches the memory cell access transistor which is to be enabled from the word line. The word line driving voltage is applied to the sample transistor, and when it begins to conduct current indicating that its threshold of operation has been reached, a current mirror provides an output voltage which is used in a feedback loop to inhibit operation of the voltage pump. Since the sample transistor is identical to the memory access transistor, the exactly correct word line driving voltage is maintained.
Thus accurate regulation of the boosted word line voltage is produced, without the danger of damaging voltages. Because once the correct word line driving voltage is reached, the voltage pump is inhibited, there is no additional power required to charge voltage boosting capacitors higher than this point, saving power. Since the voltage that is exactly that required is generated, improved reliability is achieved because double boot-strap voltages on the chip are eliminated. The circuit is thus of high efficiency.
The first and second embodiments are preferred to be used together, achieving the advantages of both.
The same basic design could also be employed as a negative substrate back-bias voltage (Vbb) generator.
An embodiment of the invention is a boosted voltage supply comprising a D.C. voltage supply terminal, first and second capacitors, the first capacitor having one terminal connected to ground and its other terminal to an output terminal, switching apparatus for connecting one terminal of the second capacitor alternately between the voltage supply terminal and ground and connecting the other terminal of the second capacitor alternately between the voltage supply terminal and the output terminal, whereby a boosted voltage regulated to the D.C. voltage supply is provided at the output terminal.
Another embodiment of the invention is a dynamic random access (DRAM) word line supply comprising an increasing voltage supply for the word line for connection to the word line from time to time, a memory cell access transistor for connecting a memory cell capacitor to a bit line having a gate connected to the word line, a sample transistor similar to the memory cell access transistor, apparatus for applying the voltage supply to the sample transistor for turning on the sample transistor at a supply voltage related to the characteristics of the sample transistor, and apparatus for inhibiting increase of the voltage supply upon turn-on of the sample transistor, whereby a voltage supply having a voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line.